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ICS840004I-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS840004I-01 is a 4 output LVCMOS/LVTTL Synthesizer optimized to generate Ethernet HiPerClockSTM reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from IDT. Using a 25MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL1:0): 156.25MHz, 125MHz, and 62.5MHz. The ICS840004I-01 uses IDT's 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical random rms phase jitter, easily meeting Ethernet jitter requirements. The ICS840004I-01 is packaged in a small 20-pin TSSOP package.
FEATURES
* Four LVCMOS/LVTTL outputs, 17 typical output impedance * Selectable crystal oscillator interface or LVCMOS single-ended input * Supports the following output frequencies: 156.25MHz, 125MHz and 62.5MHz * VCO range: 560MHz - 700MHz * RMS phase jitter @ 156.25MHZ (1.875MHz - 20MHz): 0.52ps (typical) * Output supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V * -40C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead-free RoHS (6) packages
IC S
FREQUENCY SELECT FUNCTION TABLE
F_SEL1 F_SEL0 0 0 1 1 0 1 0 1 Inputs M Divider N Divider Value Value 25 4 25 25 25 5 10 5 M/N Ratio Value 6.25 5 2.5 5 Output Frequency (MHz) (25MHz Ref.) 156.25 125 62.5 125 (default)
BLOCK DIAGRAM
OE Pullup F_SEL1:0 Pullup:Pullup nPLL_SEL Pulldown nXTAL_SEL XTAL_IN Pulldown 25MHz
PIN ASSIGNMENT
2
F_SEL0 nc nXTAL_SEL REF_CLK OE MR nPLL_SEL VDDA nc VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 F_SEL1 GND Q0 Q1 VDDO Q2 Q3 GND XTAL_IN XTAL_OUT
OSC
XTAL_OUT REF_CLK Pulldown
0
F_SEL1:0
1 Phase Detector
00 01 10 11
Q0
1
VCO
0
N /4 /5 /10 /5 (default)
Q1
ICS840004I-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
Q2
M = /25 (fixed)
Q3
G Package Top View
MR
840004AGI-01
Pulldown
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REV. A OCTOBER 22, 2007
ICS840004I-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number 1, 20 2, 9 3 4 5 6 Name F_SEL0, F_SEL1 nc nXTAL_SEL REF_CLK OE MR Type Input Unused Input Input Input Input Pulldown Pulldown Pullup Pulldown Pullup Description Frequency select pin. LVCMOS/LVTTL interface levels. No connect. Selects between the cr ystal or REF_CLK inputs as the PLL reference source. When HIGH, selects REF_CLK. When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels. Single-ended LVCMOS/LVTTL reference clock input. Output enable pin. When HIGH, the outputs are active. When LOW, the outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the otuputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL Bypass. When LOW, the output is driven from the VCO output. When HIGH, the PLL is bypassed and the output frequency = reference clock frequency/N output divider. LVCMOS/LVTTL interface levels. Analog supply pin. Core supply pin. Cr ystal oscillator interface. XTAL_OUT is the output. XTAL_IN is the input. Power supply ground. Single-ended clock outputs. LVCMOS/LVTTL interface levels. 17 typical output impedance. Output supply pin.
7 8 10 11, 12 13, 19 14, 15 17, 18 16
nPLL_SEL VDDA VDD XTAL_OUT, XTAL_IN GND Q3, Q2, Q1, Q0 VDDO
Input Power Power Input Power Output Power
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance Input Pullup Resistor Input Pulldown Resistor Output Impedance VDDO = 3.3V5% VDDO = 2.5V5% Test Conditions Minimum Typical 4 8 51 51 17 21 Maximum Units pF pF k k
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FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V 73.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDDD = VDDA = 3.3V5%, VDDO = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 2.375 Typical 3.3 3.3 3.3 2.5 Maximum 3.465 3.465 3.465 2.625 100 12 10 Units V V V V mA mA mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = -40C TO 85C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 2.375 Typical 2.5 2.5 2.5 Maximum 2.625 2.625 2.625 95 12 8 Units V V V mA mA mA
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FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5% OR 2.5V5%, OR
VDD = VDDA = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C
Symbol Parameter VIH VIL Input High Voltage Input Low Voltage OE, F_SEL0:1 nPLL_SEL, MR, nXTAL_SEL, REF_CLK OE, F_SEL0:1 IIL Input Low Current nPLL_SEL, MR, nXTAL_SEL, REF_CLK Test Conditions VDD = 3.3V VDD = 2.5V VDD = 3.3V VDD = 2.5V VDD = VIN = 3.465V or 2.625V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.5V, VIN = 0V VDD = 3.465V or 2.5V, VIN = 0V VDDO = 3.3V 5% VDDO = 2.5V 5% VDDO = 3.3V or 2.5V 5% Minimum Typical 2 1.7 -0.3 -0.3 Maximum VDD + 0.3 VDD + 0.3 0.8 0.7 5 150 -150 -5 2.6 1.8 0.5 Units V V V V A A A A V V V
IIH
Input High Current
VOH VOL
Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant cr ystal. Test Conditions Minimum Typical 25 50 7 1 Maximum Units MHz pF mW Fundamental
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol fOUT t sk(o) t jit(O) t R / tF odc Parameter Output Frequency Output Skew; NOTE 1, 2 156.25MHz, (1.875MHz - 20MHz) RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time Output Duty Cycle 125MHz, (1.875MHz - 20MHz) 62.5MHz, (1.875MHz - 20MHz) 20% to 80% F_SEL[1:0] = 00 or 01 200 43 0.52 0.65 0.55 700 57 51 Test Conditions F_SEL[1:0] = 00 F_SEL[1:0] = 01 or 11 F_SEL[1:0] = 10 Minimum 140 112 56 Typical 156.25 125 62.5 Maximum 175 140 70 60 Units MHz MHz MHz ps ps ps ps ps % %
F_SEL[1:0] = 10 or 11 49 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot.
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REV. A OCTOBER 22, 2007
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FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C
Symbol fOUT t sk(o) t jit(O) t R / tF odc Parameter Output Frequency Output Skew; NOTE 1, 2 156.25MHz, (1.875MHz - 20MHz) RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time Output Duty Cycle 125MHz, (1.875MHz - 20MHz) 62.5MHz, (1.875MHz - 20MHz) 20% to 80% F_SEL[1:0] = 00 or 01 200 43 0.48 0.59 0.53 700 57 51 Test Conditions F_SEL[1:0] = 00 F_SEL[1:0] = 01 or 11 F_SEL[1:0] = 10 Minimum 140 112 56 Typical 156.25 125 62.5 Maximum 175 140 70 60 Units MHz MHz MHz ps ps ps ps ps % %
F_SEL[1:0] = 10 or 11 49 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot.
TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = -40C TO 85C
Symbol fOUT t sk(o) t jit(O) t R / tF odc Parameter Output Frequency Output Skew; NOTE 1, 2 156.25MHz, (1.875MHz - 20MHz) RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time Output Duty Cycle 125MHz, (1.875MHz - 20MHz) 62.5MHz, (1.875MHz - 20MHz) 20% to 80% F_SEL[1:0] = 00 or 01 200 44 0.50 0.60 0.51 700 56 51 Test Conditions F_SEL[1:0] = 00 F_SEL[1:0] = 01 or 11 F_SEL[1:0] = 10 Minimum 140 112 56 Typical 156.25 125 62.5 Maximum 175 140 70 60 Units MHz MHz MHz ps ps ps ps ps % %
F_SEL[1:0] = 10 or 11 49 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot.
840004AGI-01
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REV. A OCTOBER 22, 2007
ICS840004I-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE
0 -10 -20 -30 -40 -50
AT
62.5MHZ @3.3V
1Gb Ethernet Filter 62.5MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.55ps
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110
Raw Phase Noise Data
-120 -130 -140 -150 -170 -180 -190 100 1k -160
Phase Noise Result by adding 1Gb Ethernet Filter to raw data
10k 100k 1M 10M 100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE
0 -20 -30 -40 -50 -10
AT
62.5MHZ @2.5V
1Gb Ethernet Filter 62.5MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.51ps
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k
6
Raw Phase Noise Data
Phase Noise Result by adding 1Gb Ethernet Filter to raw data
100k 1M 10M 100M
REV. A OCTOBER 22, 2007
OFFSET FREQUENCY (HZ)
840004AGI-01
ICS840004I-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE
0 -20 -30 -40 -50 -10
AT
125MHZ @3.3V
10Gb Ethernet Filter 125MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.65ps (typical)
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -170 -180 -190 100 1k 10k -160
Raw Phase Noise Data
Phase Noise Result by adding 10Gb Ethernet Filter to raw data
100k 1M 10M 100M
TYPICAL PHASE NOISE
0 -20 -30 -40 -50 -10
10Gb Ethernet Filter 125MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.60ps (typical)
OFFSET FREQUENCY (HZ)
AT
125MHZ @2.5V
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110
Raw Phase Noise Data
-120 -130 -140 -150 -160 -170 -180 -190 100
840004AGI-01
Phase Noise Result by adding 10Gb Ethernet Filter to raw data
1k 10k
7
100k
1M
10M
100M
REV. A OCTOBER 22, 2007
OFFSET FREQUENCY (HZ)
ICS840004I-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE
0 -20 -30 -40 -50 -10
AT
156.25MHZ @3.3V
10Gb Ethernet Filter 156.25MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.52ps (typical)
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -170 -180 -190 100 1k 10k -160
Raw Phase Noise Data
Phase Noise Result by adding 10Gb Ethernet Filter to raw data
100k 1M 10M 100M
TYPICAL PHASE NOISE
0 -20 -30 -40 -50 -10
10Gb Ethernet Filter 156.25MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.50ps (typical)
OFFSET FREQUENCY (HZ)
AT
156.25MHZ @2.5V
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -170 -180 -190 100 1k 10k
8
Raw Phase Noise Data
Phase Noise Result by adding 10Gb Ethernet Filter to raw data
100k 1M 10M 100M
REV. A OCTOBER 22, 2007
-160
OFFSET FREQUENCY (HZ)
840004AGI-01
ICS840004I-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION
1.65V5%
VDDA = 1.65V5%
2.05V5% VDDA = 2.05V5% 1.25V5%
VDD, VDDO
SCOPE
VDD
Qx
SCOPE
VDDO
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
1.25V5%
VDDA = 1.25V5%
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
VDD, VDDO
Noise Power
SCOPE
Qx
LVCMOS
GND
Phase Noise Mask
f1
Offset Frequency
f2
-1.25V5%
RMS Jitter = Area Under the Masked Phase Noise Plot
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
V
DDO
RMS PHASE JITTER
80% 20% tR tF 80% 20%
Qx
2
V
DDO
Clock Outputs
Qy
2 tsk(o)
OUTPUT SKEW
V
DDO
OUTPUT RISE/FALL TIME
Q0:Q3 t PW
t
2
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
840004AGI-01 9 REV. A OCTOBER 22, 2007
ICS840004I-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840004I-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA.
3.3V or 2.5V VDD .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840004I-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS84332
ICS840004I-01
FIGURE 2. CRYSTAL INPUt INTERFACE
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FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output
VDD
impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD
R1 Ro Rs Zo = 50 .1uf XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. REF_CLK INPUT For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_CLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVCMOS OUTPUTS All unused LVCMOS output can be left floating. We recommend that there is no trace attached.
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REV. A OCTOBER 22, 2007
ICS840004I-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
LAYOUT GUIDELINE
Figure 4 shows a schematic example of the ICS840004I01. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18pF parallel resonant 25MHz crystal is used. The C1=22pF and C2=22pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. 1k pullup or pulldown resistors can be used for the logic control input pins.
Logic Control Input Examples
VDD
Set Logic Input to '1'
RU1 1K
VDD
Set Logic Input to '0'
RU2 Not Install
VDD=3.3V VDDO=3.3V
R3 36 Zo = 50 Ohm
To Logic Input pins
RD1 Not Install RD2 1K
To Logic Input pins
U1 VDDO 1 2 3 4 5 6 7 8 9 10 F_SEL0 nc nXTAL_SEL REF_CLK OE MR nPLL_SEL VDDA nc VDD F_SEL1 GND Q0 Q1 VDDO Q2 Q3 GND XTAL_IN XTAL_OUT 20 19 18 17 16 15 14 13 12 11 Zo = 50 Ohm 840004i_01 XTAL_OUT C2 22pF X1 XTAL_IN C5 0.1u R4 100 LVCMOS LVCMOS
VDD VDD VDDA R2 10 C3 10uF VDD C4 0.01u C6 0.1u
VDD R5 100
If not using the crystal input, it can be left floating. For additional protection the XTAL_IN pin can be tied to ground.
C1 22pF
Optional Termination Unused outputs can be left floating. There should be no trace attached to unused outputs. Device characterized and specification limits set with all outputs terminated.
FIGURE 4. ICS840004I-01 SCHEMATIC EXAMPLE
840004AGI-01
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REV. A OCTOBER 22, 2007
ICS840004I-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS840004I-01 is: 3796
840004AGI-01
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REV. A OCTOBER 22, 2007
ICS840004I-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX
FOR
20 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
SYMBOL MIN N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 20 1.20 0.15 1.05 0.30 0.20 6.60 Millimeters MAX
Reference Document: JEDEC Publication 95, MO-153
840004AGI-01 14 REV. A OCTOBER 22, 2007
ICS840004I-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS840004AGI-01 ICS840004AGI-01T ICS840004AGI-01lLF ICS840004AGI-01LFT Marking ICS40004AI01 ICS40004AI01 ICS0004AI01L ICS0004AI01L Package 20 Lead TSSOP 20 Lead TSSOP 20 Lead "Lead-Free" TSSOP 20 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
NOTE: Par ts that are ordered with an "LF" suffix tot he par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 840004AGI-01 15 REV. A OCTOBER 22, 2007
ICS840004I-01
FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
REVISION HISTORY SHEET Rev A Table T8 Page 15 Description of Change Ordering Informatin Table - corrected standard marking and added Lead Free marking. Date 10/22/07
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REV. A OCTOBER 22, 2007

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